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M48Z35 M48Z35Y
256 Kbit (32Kb x8) ZEROPOWER(R) SRAM
s
INTEGRATED ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT and BATTERY READ CYCLE TIME EQUALS WRITE CYCLE TIME AUTOMATIC POWER-FAIL CHIP DESELECT and WRITE PROTECTION WRITE PROTECT VOLTAGES (VPFD = Power-fail Deselect Voltage): - M48Z35: 4.50V VPFD 4.75V - M48Z35Y: 4.20V VPFD 4.50V SELF-CONTAINED BATTERY in the CAPHAT DIP PACKAGE PACKAGING INCLUDES a 28-LEAD SOIC and SNAPHAT(R) TOP (to be Ordered Separately) SOIC PACKAGE PROVIDES DIRECT CONNECTION for a SNAPHAT TOP which CONTAINS the BATTERY and CRYSTAL PIN and FUNCTION COMPATIBLE with JEDEC STANDARD 32K x8 SRAMs
SNAPHAT (SH) Battery
s
s
s
28
28 1
1
PCDIP28 (PC) Battery CAPHAT
s
SOH28 (MH)
s
Figure 1. Logic Diagram
s
s
VCC
DESCRIPTION The M48Z35/35Y ZEROPOWER (R) RAM is a 32 Kbit x8 non-volatile static RAM that integrates power-fail deselect circuitry and battery control logic on a single die. The monolithic chip is available in two special packages to provide a highly integrated battery backed-up memory solution.
15 A0-A14
8 DQ0-DQ7
W E
M48Z35 M48Z35Y
Table 1. Signal Names
A0-A14 DQ0-DQ7 E G W VCC VSS Address Inputs Data Inputs / Outputs Chip Enable Output Enable Write Enable Supply Voltage Ground
G
VSS
AI01616D
August 1999
1/18
M48Z35, M48Z35Y
Figure 2A. DIP Pin Connections Figure 2B. SOIC Pin Connections
A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS
28 1 27 2 26 3 25 4 24 5 23 6 7 M48Z35 22 8 M48Z35Y 21 20 9 19 10 18 11 17 12 13 16 14 15
AI01617D
VCC W A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3
A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS
1 28 27 2 26 3 25 4 24 5 23 6 22 7 M48Z35Y 21 8 20 9 19 10 18 11 17 12 16 13 15 14
AI02303C
VCC W A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3
Table 2. Absolute Maximum Ratings (1)
Symbol TA TSTG TSLD (2) VIO VCC IO PD Parameter Ambient Operating Temperature Storage Temperature (VCC Off) Grade 1 Grade 6 SNAPHAT SOIC Value 0 to 70 -40 to 85 -40 to 85 -55 to 125 260 -0.3 to 7 -0.3 to 7 20 1 Unit C C C V V mA W
Lead Solder Temperature for 10 seconds Input or Output Voltages Supply Voltage Output Current Power Dissipation
Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect reliability. 2. Soldering temperature not to exceed 260C for 10 seconds (total thermal budget not to exceed 150C for longer than 30 seconds).
CAUTION: Negative undershoots below -0.3V are not allowed on any pin while in the Battery Back-up mode. CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
2/18
M48Z35, M48Z35Y
Table 3. Operating Modes (1)
Mode Deselect Write Read Read Deselect Deselect VSO to VPFD (min) (2) VSO 4.75V to 5.5V or 4.5V to 5.5V VCC E VIH VIL VIL VIL X X G X X VIL VIH X X W X VIL VIH VIH X X DQ0-DQ7 High Z DIN DOUT High Z High Z High Z Power Standby Active Active Active CMOS Standby Battery Back-up Mode
Note: 1. X = VIH or VIL; VSO = Battery Back-up Switchover Voltage. 2. See Table 7 for details.
Figure 3. Block Diagram
A0-A14
LITHIUM CELL VOLTAGE SENSE AND SWITCHING CIRCUITRY
POWER
32K x 8 SRAM ARRAY
DQ0-DQ7
VPFD
E W G
VCC
VSS
AI01619B
The M48Z35/35Y is a non-volatile pin and function equivalent to any JEDEC standard 32K x8 SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets, providing the non-volatility of PROMs without any requirement for special write timing or limitations on the number of writes that can be performed. The 28 pin 600mil DIP CAPHATTM houses the M48Z35/35Y silicon with a long life lithium button cell in a single package. The 28 pin 330mil SOIC provides sockets with gold plated contacts at both ends for direct con-
nection to a separate SNAPHAT housing containing the battery. The unique design allows the SNAPHAT battery package to be mounted on top of the SOIC package after the completion of the surface mount process. Insertion of the SNAPHAT housing after reflow prevents potential battery damage due to the high temperatures required for device surface-mounting. The SNAPHAT housing is keyed to prevent reverse insertion.
3/18
M48Z35, M48Z35Y
Table 4. AC Measurement Conditions
Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages 5ns 0 to 3V 1.5V
DEVICE UNDER TEST 645
Figure 4. AC Testing Load Circuit
Note that Output Hi-Z is defined as the point where data is no longer driven.
The SOIC and battery packages are shipped separately in plastic anti-static tubes or in Tape & Reel form. For the 28 lead SOIC, the battery package (i.e. SNAPHAT) part number is "M4Z28-BR00SH1". The M48Z35/35Y also has its own Power-fail Detect circuit. The control circuitry constantly monitors the single 5V supply for an out of tolerance condition. When VCC is out of tolerance, the circuit write protects the SRAM, providing a high degree of data security in the midst of unpredictable system operation brought on by low V CC. As VCC falls below approximately 3V, the control circuitry connects the battery which maintains data until valid power returns. READ MODE The M48Z35/35Y is in the Read Mode whenever W (Write Enable) is high, E (Chip Enable) is low. The device architecture allows ripple-through access of data from eight of 264,144 locations in the static storage array. Thus, the unique address specified by the 15 Address Inputs defines which one of the 32,768 bytes of data is to be accessed. Valid data will be available at the Data I/O pins within Address Access time (tAVQV) after the last address input signal is stable, providing that the E and G access times are also satisfied. If the E and G access times are not met, valid data will be available after the latter of the Chip Enable Access time (tELQV) or Output Enable Access time (tGLQV). The state of the eight three-state Data I/O signals is controlled by E and G. If the outputs are activat-
CL = 100pF or 5pF
1.75V
CL includes JIG capacitance
AI03211
ed before t AVQV, the data lines will be driven to an indeterminate state until tAVQV. If the Address Inputs are changed while E and G remain active, output data will remain valid for Output Data Hold time (tAXQX) but will go indeterminate until the next Address Access. WRITE MODE The M48Z35/35Y is in the Write Mode whenever W and E are low. The start of a write is referenced from the latter occurring falling edge of W or E. A write is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W must return high for a minimum of tEHAX from Chip Enable or tWHAX from Write Enable prior to the initiation of another read or write cycle. Data-in must be valid tDVWH prior to the end of write and remain valid for t WHDX afterward. G should be kept high during write cycles to avoid bus contention; although, if the output bus has been activated by a low on E and G, a low on W will disable the outputs tWLQZ after W falls.
4/18
M48Z35, M48Z35Y
Table 5. Capacitance (1, 2) (TA = 25 C)
Symbol CIN CIO (3) Parameter Input Capacitance Input / Output Capacitance Test Condition VIN = 0V VOUT = 0V Min Max 10 10 Unit pF pF
Note: 1. Effective capacitance measured with power supply at 5V. 2. Sampled only, not 100% tested. 3. Outputs deselected.
Table 6. DC Characteristics (TA = 0 to 70 C or -40 to 85 C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
Symbol ILI (1) ILO (1) ICC ICC1 ICC2 VIL (2) VIH VOL VOH Parameter Input Leakage Current Output Leakage Current Supply Current Supply Current (Standby) TTL Supply Current (Standby) CMOS Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IOL = 2.1mA IOH = -1mA 2.4 Test Condition 0V VIN VCC 0V VOUT VCC Outputs open E = VIH E = VCC - 0.2V -0.3 2.2 Min Max 1 5 50 3 3 0.8 VCC + 0.3 0.4 Unit A A mA mA mA V V V V
Note: 1. Outputs deselected. 2. Negative spikes of -1V allowed for up to 10ns once per cycle.
Table 7. Power Down/Up Trip Points DC Characteristics (1) (TA = 0 to 70 C or -40 to 85 C)
Symbol VPFD VPFD VSO tDR (2) Parameter Power-fail Deselect Voltage (M48Z35) Power-fail Deselect Voltage (M48Z35Y) Battery Back-up Switchover Voltage (M48Z35/35Y) Expected Data Retention Time 10 Min 4.5 4.2 Typ 4.6 4.35 3.0 Max 4.75 4.5 Unit V V V YEARS
Note: 1. All voltages referenced to VSS. 2. At 25 C.
5/18
M48Z35, M48Z35Y
Table 8. Power Down/Up AC Characteristics (TA = 0 to 70 C or -40 to 85 C)
Symbol tPD tF (1) tFB (2) tR tRB tREC (3) Parameter E or W at VIH before Power Down VPFD (max) to VPFD (min) VCC Fall Time VPFD (min) to VSS VCC Fall Time VPFD (min) to VPFD (max) VCC Rise Time VSS to VPFD (min) VCC Rise Time VPFD (max) to Inputs Recognized Min 0 300 10 10 1 40 200 Max Unit s s s s s ms
Note: 1. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200s after VCC passes V PFD (min). 2. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data. 3. tREC (min) = 20ms for industrial temperature grade (6) device.
Figure 5. Power Down/Up Mode AC Waveforms
VCC VPFD (max) VPFD (min) VSO tF tFB tPD INPUTS
RECOGNIZED
tR tRB tDR DON'T CARE tREC
RECOGNIZED
HIGH-Z OUTPUTS VALID
(PER CONTROL INPUT)
VALID
(PER CONTROL INPUT)
AI01168C
6/18
M48Z35, M48Z35Y
Table 9. Read Mode AC Characteristics (TA = 0 to 70 C or -40 to 85 C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
M48Z35 / M48Z35Y Symbol Parameter Min tAVAV tAVQV (1) tELQV (1) tGLQV (1) tELQX (2) tGLQX (2) tEHQZ (2) tGHQZ (2) tAXQX (1) Read Cycle Time Address Valid to Output Valid Chip Enable Low to Output Valid Output Enable Low to Output Valid Chip Enable Low to Output Transition Output Enable Low to Output Transition Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition 10 5 5 25 25 70 70 70 35 -70 Max ns ns ns ns ns ns ns ns ns Unit
Note: 1. CL = 100pF (see Figure 4). 2. CL = 5pF (see Figure 4).
Figure 6. Read Mode AC Waveforms.
tAVAV A0-A14 tAVQV tELQV E tELQX tGLQV G tGLQX DQ0-DQ7 VALID
AI00925
VALID tAXQX tEHQZ
tGHQZ
Note: Write Enable (W) = High.
7/18
M48Z35, M48Z35Y
Table 10. Write Mode AC Characteristics (TA = 0 to 70 C or -40 to 85 C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
M48Z35 / M48Z35Y Symbol Parameter Min tAVAV tAVWL tAVEL tWLWH tELEH tWHAX tEHAX tDVWH tDVEH tWHDX tEHDX tWLQZ (1, 2) tAVWH tAVEH tWHQX (1, 2) Write Cycle Time Address Valid to Write Enable Low Address Valid to Chip Enable Low Write Enable Pulse Width Chip Enable Low to Chip Enable High Write Enable High to Address Transition Chip Enable High to Address Transition Input Valid to Write Enable High Input Valid to Chip Enable High Write Enable High to Input Transition Chip Enable High to Input Transition Write Enable Low to Output Hi-Z Address Valid to Write Enable High Address Valid to Chip Enable High Write Enable High to Output Transition 60 60 5 70 0 0 50 55 0 0 30 30 5 5 25 -70 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Note: 1. CL = 5pF (see Figure 4). 2. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
DATA RETENTION MODE With valid VCC applied, the M48Z35/35Y operates as a conventional BYTEWIDETM static RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write protecting itself when VCC falls within the VPFD(max), VPFD(min) window. All outputs become high impedance, and all inputs are treated as "don't care." Note: A power failure during a write cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the RAM's content. At voltages below VPFD(min), the user can be assured the memory will be in a write protected state, provided the VCC fall time is not less than tF. The M48Z35/35Y may respond to transient noise spikes on VCC that reach into the deselect window during the time the device is sampling V CC. There-
fore, decoupling of the power supply lines is recommended. When V CC drops below VSO, the control circuit switches power to the internal battery which preserves data. The internal button cell will maintain data in the M48Z35/35Y for an accumulated period of at least 10 years (at 25C) when VCC is less than V SO. As system power returns and V CC rises above VSO, the battery is disconnected, and the power supply is switched to external VCC. Write protection continues until V CC reaches VPFD(min) plus tREC(min). Normal RAM operation can resume tREC after VCC exceeds VPFD(max). For more information on Battery Storage Life refer to the Application Note AN1012.
8/18
M48Z35, M48Z35Y
Figure 7. Write Enable Controlled, Write AC Waveform
tAVAV A0-A14 VALID tAVWH tAVEL E tWLWH tAVWL W tWLQZ tWHDX DQ0-DQ7 DATA INPUT tDVWH
AI00926
tWHAX
tWHQX
Figure 8. Chip Enable Controlled, Write AC Waveforms
tAVAV A0-A14 VALID tAVEH tAVEL E tAVWL W tEHDX DQ0-DQ7 DATA INPUT tDVEH
AI00927
tELEH
tEHAX
9/18
M48Z35, M48Z35Y
POWER SUPPLY DECOUPLING and UNDERSHOOT PROTECTION ICC transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if capacitors are used to store energy, which stabilizes the V CC bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1F (as shown in Figure 9) is recommended in order to provide the needed filtering. In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on V CC that drive it to values below V SS by as much as one Volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, it is recommended to connect a schottky diode from V CC to VSS (cathode connected to VCC, anode to VSS). Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount. Figure 9. Supply Voltage Protection
VCC VCC
0.1F
DEVICE
VSS
AI02169
10/18
M48Z35, M48Z35Y
Table 11. Ordering Information Scheme
Example: Supply Voltage and Write Protect Voltage 35 (1) = VCC = 4.75V to 5.5V; VPFD = 4.5V to 5.5V 35Y = VCC = 4.5V to 5.5V; VPFD = 4.2V to 4.5V Speed -70 = 70ns Package PC = PCDIP28 MH (2, 3) = SOH28 Temperature Range 1 = 0 to 70 C 6 (4) = -40 to 85 C Shipping Method for SOIC blank = Tubes TR = Tape & Reel M48Z35Y -70 MH 1 TR
Note: 1. The M48Z35 part is offered with the PCDIP28 (CAPHAT) package only. 2. The SOIC package (SOH28) requires the battery package (SNAPHAT) which is ordered separately under the part number "M4Zxx-BR00SH1" in plastic tube or "M4Zxx-BR00SH1TR" in Tape & Reel form. 3. Delivery may include either the 2-pin version of the SOIC/SNAPHAT or the 4-pin version of the SOIC/SNAPHAT. Both are function ally equivalent (see package drawing section for details). 4. Industrial temperature grade available in SOIC package (SOH28) only. Caution: Do not place the SNAPHAT battery package "M4Z28-BR00SH1" in conductive foam since will drain the lithium button-cell battery.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you.
11/18
M48Z35, M48Z35Y
Table 12. PCDIP28 - 28 pin Plastic DIP, battery CAPHAT, Package Mechanical Data
mm Symb Typ A A1 A2 B B1 C D E e1 e3 eA L N Min 8.89 0.38 8.38 0.38 1.14 0.20 39.37 17.83 2.29 29.72 15.24 3.05 28 Max 9.65 0.76 8.89 0.53 1.78 0.31 39.88 18.34 2.79 36.32 16.00 3.81 Typ Min 0.350 0.015 0.330 0.015 0.045 0.008 1.550 0.702 0.090 1.170 0.600 0.120 28 Max 0.380 0.030 0.350 0.021 0.070 0.012 1.570 0.722 0.110 1.430 0.630 0.150 inches
Figure 10. PCDIP28 - 28 pin Plastic DIP, battery CAPHAT, Package Outline
A2
A
A1 B1 B e3 D
N
L eA
C
e1
E
1 PCDIP
Drawing is not to scale.
12/18
M48Z35, M48Z35Y
Table 13. SOH28 - 28 lead Plastic Small Outline, 4-socket battery SNAPHAT, Package Mechanical Data
mm Symb Typ A A1 A2 B C D E e eB H L N CP 1.27 0.05 2.34 0.36 0.15 17.71 8.23 - 3.20 11.51 0.41 0 28 0.10 Min Max 3.05 0.36 2.69 0.51 0.32 18.49 8.89 - 3.61 12.70 1.27 8 0.050 0.002 0.092 0.014 0.006 0.697 0.324 - 0.126 0.453 0.016 0 28 0.004 Typ Min Max 0.120 0.014 0.106 0.020 0.012 0.728 0.350 - 0.142 0.500 0.050 8 inches
Figure 11. SOH28 - 28 lead Plastic Small Outline, 4-socket battery SNAPHAT, Package Outline
A2 B e
A C eB CP
D
N
E
H A1 L
1 SOH-A
Drawing is not to scale.
13/18
M48Z35, M48Z35Y
Table 14. SOH28 - 28 lead Plastic Small Outline, 2-socket battery SNAPHAT, Package Mechanical Data
mm Symb Typ A A1 A2 B C D E e eB H L N CP 1.27 0.05 2.34 0.36 0.15 17.71 8.23 - 3.20 11.51 0.41 0 28 0.10 Min Max 3.05 0.36 2.69 0.51 0.32 18.49 8.89 - 3.61 12.70 1.27 8 0.050 0.002 0.092 0.014 0.006 0.697 0.324 - 0.126 0.453 0.016 0 28 0.004 Typ Min Max 0.120 0.014 0.106 0.020 0.012 0.728 0.350 - 0.142 0.500 0.050 8 inches
Figure 12. SOH28 - 28 lead Plastic Small Outline, 2-socket battery SNAPHAT, Package Outline
A2 B e
A C eB CP
D
N
E
H A1 L
1 SOH-B
Drawing is not to scale.
14/18
M48Z35, M48Z35Y
Table 15. SH - 4-pin SNAPHAT Housing for 49 mAh Battery, Package Mechanical Data
mm Symb Typ A A1 A2 A3 B D E eA eB L 0.46 21.21 14.22 15.55 3.20 2.03 6.73 6.48 Min Max 9.78 7.24 6.99 0.38 0.56 21.84 14.99 15.95 3.61 2.29 0.018 0.835 0.560 0.612 0.126 0.080 0.265 0.255 Typ Min Max 0.385 0.285 0.275 0.015 0.022 0.860 0.590 0.628 0.142 0.090 inches
Figure 13. SH - 4-pin SNAPHAT Housing for 49 mAh Battery, Package Outline
A1
A2 A A3
eA D
B eB
L
E
SHZP-A
Drawing is not to scale.
15/18
M48Z35, M48Z35Y
Table 16. SH - 2-pin SNAPHAT Housing for 49 mAh Battery, Package Mechanical Data
mm Symb Typ A A1 A2 A3 B D E eB L 0.46 21.21 14.22 3.20 2.03 6.73 6.48 Min Max 9.78 7.24 6.99 0.38 0.56 21.84 14.99 3.61 2.29 0.018 0.835 0.560 0.126 0.080 0.265 0.255 Typ Min Max 0.385 0.285 0.275 0.015 0.022 0.860 0.590 0.142 0.090 inches
Figure 14. SH - 2-pin SNAPHAT Housing for 49 mAh Battery, Package Outline
A1
A2 A A3
B D eB
L
E
SHZP-B
Drawing is not to scale.
16/18
M48Z35, M48Z35Y
Table 17. SH - 2-pin SNAPHAT Housing for 130 mAh Battery, Package Mechanical Data
mm Symb Typ A A1 A2 A3 B D E eB L 0.46 21.21 17.27 3.20 2.03 8.00 7.24 Min Max 10.54 8.51 8.00 0.38 0.56 21.84 18.03 3.61 2.29 0.018 0.835 0.680 0.126 0.080 0.315 0.285 Typ Min Max 0.415 0.335 0.315 0.015 0.022 0.860 0.710 0.142 0.090 inches
Figure 15. SH - 2-pin SNAPHAT Housing for 130 mAh Battery, Package Outline
A1
A2 A A3
B D eB
L
E
SHZP-B
Drawing is not to scale.
17/18
M48Z35, M48Z35Y
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics (R) 1999 STMicroelectronics - All Rights Reserved All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
18/18

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